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| QS5820T GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER COMMERCIAL TEMPERATURE RANGE GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER FEATURES: * * * * * * 20 output, low skew clock signal buffer High drive FCT-type outputs Reduced swing TTL outputs for low noise Input hysteresis for better noise margin Monitor output Guaranteed low skew - 0.5ns output skew - 0.7ns pulse skew - 1ns part-to-part skew Available in 40-pin QVSOP QS5820T DESCRIPTION: The QS5820T clock driver/buffer circuits can be used for clock distribution schemes where low skew, high speed, and small footprint are primary concerns. The QS5820T offers four banks of five non-inverting outputs. Designed in IDT's proprietary QCMOS process, this device provides low propagation delay buffering with on-chip skew of 0.5ns for same-transition, same-bank signals. The QS5820T provides major skew advantages over octal type devices where total part-to-part skew (tSK(t)) of >1ns is unacceptable. Furthermore, board area consumed by the QVSOP package is almost one-third that of the typical SOIC package offered for octal devices. This clock buffer product is designed for use in high performance workstation, multi-board computing and telecommunications systems. The QS5820T is available in the 40-pin QVSOP package which offers the world's smallest logic footprint. * FUNCTIONAL BLOCK DIAGRAM OE A 5 IN A OA1-O A5 OE B 5 IN B OB1-O B5 MONB OEC 5 INC OC1-OC 5 OED 5 IND OD1-OD 5 MO ND COMMERCIAL TEMPERATURE RANGE 1 c 2000 Integrated Device Technology, Inc. DECEMBER 2000 DSC-5822/- QS5820T GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION VDD OA1 OA2 OA3 GND OA4 OA5 GND OEA IN A VD D OC1 OC2 OC3 GND OC4 OC5 GND OE C INC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SO 40-1 31 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 VDD OB1 OB2 OB3 GN D OB4 OB5 MO N B OEB IN B VDD OD1 OD2 OD3 GN D OD4 OD5 MO ND OED IND ABSOLUTE MAXIMUM RATINGS Symbol VTERM(2) VTERM(3) VTERM(3) VAC IOUT PMAX TSTG Rating Supply Voltage to Ground DC Switch Voltage VS DC Input Voltage VIN AC Input Voltage (pulse width 20ns) DC Input Diode Current with VIN < 0 DC Output Current Max Sink Current/Pin Maximum Power Dissipation Storage Temperature Range Max. -0.5 to +7 -0.5 to +7 -0.5 to +7 -3 -20 120 1.2 (1) Unit V V V V mA mA W C -65 to +150 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD Terminals. 3. All terminals except VDD. CAPACITANCE (TA = 25 C, f = 1MHz, VIN = 0V, VOUT = 0V) Pins All Pins Typ. 5 Max. 8 Unit pF NOTE: 1. Capacitance is characterized but not tested. PIN DESCRIPTION Pin Name OEA, OEB, OEC, OED INA, INB, INC, IND OAn, OBn, OCn, ODn MONB, MOND Type I I O O Description Output Enable Inputs Clock Inputs Clock Outputs Non-disable Monitor Outputs QVSOP TOP VIEW RECOMMENDED OPERATING CONDITIONS Symbol VDD VIN VOUT TA Description Power Supply Voltage Input Voltage Voltage Applied to Outputs Ambient Operating Temperature Min. 4.75 0 0 0 Max. 5.25 5.5 5.5 +70 Unit V V V C 2 QS5820T GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol VIH VIL VIC VOH VOL IIN IOZ IOS Parameter Input HIGH Voltage Input LOW Voltage Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Current Output Leakage Current Short Circuit Current (2,3) (3) Conditions Guaranteed Logic HIGH for Inputs Guaranteed Logic LOW for Inputs VDD = Min., IIN = -18mA VDD = Min., IOH = -24mA VDD = Min., IOL = 64mA VDD = Max., VIN = VDD or GND VDD = Max., Outputs High-Z VDD = Max., VOUT = GND Min. 2 -- -- 2.4 -- -- -- - 60 Typ. -- -- - 0.7 -- -- -- -- -- Max. -- 0.8 - 1.2 -- 0.55 1 1 -- Unit V V V V V A A mA NOTES: 1. Typical values are at VDD = 5.0V, TA = 25C. 2. Not more than one output should be used to test this high power condition. Duration is 1 second. 3. Guaranteed by design but not tested. POWER SUPPLY CHARACTERISTICS Symbol ICC ICC ICCD Parameter Quiescent Power Supply Current Supply Current per Input HIGH Dynamic Power Supply Current per Output (2) Test Conditions (1) VDD = Max., VIN = GND or VDD VDD = Max., VIN = 3.4V, fI = 0MHz VDD = Max., VIN = GND or VDD Outputs Enabled, 50% duty cycle Typ. (3) 0.4 0.5 0.1 Max. 3 2.5 0.2 Unit mA mA mA/MHz NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC specifications. 2. Guaranteed but not tested. 3. Typical values are for reference only. Conditions are VDD = 5.0V and TA = 25C. 4. IC = ICC + (ICC)(DH)(NT) + ICCD (fO)(NO) where: DH = Input duty cycle NT = Number of TTL HIGH inputs at DH fO = Output frequency NO = Number of outputs at fO 3 QS5820T GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER COMMERCIAL TEMPERATURE RANGE SKEW CHARACTERISTICS OVER OPERATING RANGE QS5820AT Symbol tSK(01) tSK(02) tSK(p) tSK(t) Description (1) Skew between two outputs, same transition, same bank Skew between two outputs, same transition, different bank Duty cycle distortion (pulse skew) on a single output opposite transitions (tPHL - tPLH) Part-to-part skew, same transition (2) Min. -- -- -- -- Max. 0.5 0.6 1 1.5 QS5820BT Min. -- -- -- -- Max. 0.5 0.6 0.7 1 Unit ns ns ns ns NOTES: 1. Skew parameters are guaranteed across temperature range, but not production tested. Skew parameters apply to propagation delays only. 2. tSK(t) only applies to devices of the same transition, same VDD, same temperature, same speed grade, and same loading. SWITCHING CHARACTERISTICS OVER OPERATING RANGE CLOAD = 50pF, RLOAD = 500 unless otherwise noted. QS5820AT Symbol tPLH tPHL tR tF tPZL tPZH tPLZ tPHZ Description (1) Propagation Delay (1,2) Output Rise Time, 0.8V to 2V Output Fall Time, 2V to 0.8V Output Enable Time Output Disable Time Min. 1.5 -- -- 1.5 1.5 Max. 5.8 1.5 1.5 8 7 Min. 1.5 -- -- 1.5 1.5 QS5820BT Max. 5 1.5 1.5 7 6 Unit ns ns ns ns ns NOTES: 1. Minimums guaranteed but not tested. 2. The propagation delay range indicated by Min. and Max. specifications results from process and environmental variables. These propagation delay limits do not imply skew. 4 QS5820T GUARANTEED LOW SKEW CMOS 20 OUTPUT CLOCK DRIVER/BUFFER COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION QS XXX XX Package Device Type Q2 Quarter Size Very Sm all Outline Package (SO40-1) 5820AT 5820BT Guaranteed Low Skew CM OS 20 Output Clock Driver/Buffer CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. Turboclock is a registered trademark of Integrated Device Technology, Inc. 5 |
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